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IMPORTANT NOTICE
Dear customer, As from August 2nd 2008, the wireless operations of STMicroelectronics have moved to a new company, ST-NXP Wireless. As a result, the following changes are applicable to the attached document.

Company name - STMicroelectronics NV is replaced with ST-NXP Wireless. Copyright - the copyright notice at the bottom of the last page "(c) STMicroelectronics 200x - All rights reserved", shall now read: "(c) ST-NXP Wireless 200x - All rights reserved". Web site - http://www.st.com is replaced with http://www.stnwireless.com Contact information - the list of sales offices is found at http://www.stnwireless.com under Contacts.

If you have any questions related to the document, please contact our nearest sales office. Thank you for your cooperation and understanding. ST-NXP Wireless
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STw4141
Single-coil dual-output step-down DC/DC converter for digital base band and multimedia processor supply
Features
Single coil dual output switching converter for digital core supply & digital I/Os supply - Digital I/O supply:VOUT1 @ 200 mA - CPU CORE supply:VOUT2 @ 400 mA Wide range of fixed output voltage configurations available High efficiency synchronous step down converter with up to 92 % for the entire device Size and cost optimized application board (7x8 mm, height 1.2mm) three capacitors and only one inductor necessary for both outputs 2.7 V to 5.5 V battery input range 100mV output voltage accuracy full range in PWM (Including Line and Load Transients) 900 kHz fixed frequency PWM operation PFM mode operation at light load current PWM/PFM switch can be done automatically or forced by setting external pins (AUTO and MODE/SYNC) MODE/SYNC input pin for external clock synchronization from 600 kHz to 1.5 MHz VSEL input pin for VOUT2/VOUT2(red.) selection Ultra low shutdown current (Iq<1 A) Short circuit and thermal shutdown protections

Solution size 7 x 8 mm

TFBGA 3x3mm 16 bumps 0.5 mm pitch
Applications
Mobile phones PDAs and hand held terminals Portable media players Digital still camera WLAN and Bluetooth applications

Description
The STw4141 is a single coil dual output synchronous step down DC/DC converter that requires only four standard external components. It operates at a fixed 900 kHz switching frequency in PWM mode. The device can operate in PFM mode to maintain high efficiency over the full range of output currents. The STw4141 application requires a very small PCB area and offers a very efficient, accurate, space and cost saving solution to fulfill the requirements of digital baseband or multimedia processor supply (CORE & I/O).

Application test circuit
L 4.7 H VLX1 VIN=2.7V to 5.5V CIN 10 F 6.3 V PVDD
B1 A2
VLX2
A3 A4 D1
VOUT1 FB1 COUT1 22 F 6.3 V
VOUT1=1.8V
VDD
D3
EN AUTO
D4 C2
STw4141
B4 D2 B2 B3
VOUT2 FB2 STATE COUT2 22 F 6.3 V
VOUT2=1.0V/1.2V
VSEL MODE/SYNC
C3 C1
A1
C4
PGND GND
T_MODE
June 2006
Rev 2
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1
Contents
STw4141
Contents
1 2 STw4141 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Dynamic electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Soft start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Settling time of VOUT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Line transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Load transients in AUTO mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Load transients in PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Switching between PFM and PWM in FORCED mode . . . . . . . . . . . . . . 14 Efficiency in PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Efficiency in AUTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Output voltages versus output currents in PWM and PFM . . . . . . . . . . . . 17
3
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PWM and PFM mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Current limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Thermal shutdown protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 4.2 4.3 4.4 4.5 4.6 User mode details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Automatic PWM/PFM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 User selected PWM/PFM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 External clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Checking transient response versus external components . . . . . . . . . . . 21 Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.6.1 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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STw4141 4.6.2 4.6.3 4.6.4
Contents Input capacitor (CIN selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Output capacitors (COUT selection) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Capacitors selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.7
PCB layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.7.1 4.7.2 PCB layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 TFBGA16 internal bumps access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5 6 7
Package outline and mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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List of tables
STw4141
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. STw4141 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Dynamic electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 STw4141 available user modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Operating mode information (STATE pin - digital output) . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Bill of material: inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Bill of Material: capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 TFBGA 3x3x1.20 16 F4x4 0.50. Package code: L0 - JEDEC/EAIJ . . . . . . . . . . . . . . . . . . 26 STw4141 order codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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STw4141
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Pin assignment in TFBGA 3x3 mm - 16 bumps 0.5 mm pitch . . . . . . . . . . . . . . . . . . . . . . . 6 Smooth start-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Settling time of VOUT2, IOUT1 = 200mA, IOUT2 = 400mA . . . . . . . . . . . . . . . . . . . . . . . . 11 Line transient, VOUT1 = 1.8V @ 100mA, VOUT2 = 1.2V @ 100mA . . . . . . . . . . . . . . . . . 12 Load transient in AUTO mode VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V . . . . . . . . . . . . 12 Load transient in PWM mode, IOUT1 = 1mA to 200mA, IOUT2 = 1mA to 400mA. . . . . . . 13 Switching between PFM to PWM - VIN = 3.6V, IOUT1 = 10mA, IOUT2 = 10mA. . . . . . . . 14 Switching between PWM to PFM - VIN = 3.6V, IOUT1 = 10mA, IOUT2 = 10mA. . . . . . . . 14 Switching regulator efficiency in PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Switching regulator efficiency in auto mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Output voltages versus output currents in PWM and PFM . . . . . . . . . . . . . . . . . . . . . . . . . 17 Automatic PWM/PFM switch schematic example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PWM/PFM forced mode schematic example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Application using external clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Board layout track length and width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Demoboard top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Demoboard assembled with 22 F output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 TFBGA16 ball pad spacing and track parameters to internal pads . . . . . . . . . . . . . . . . . . 24 PCB routing example using TFBGA16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 TFBGA 3x3x1.20 16 F4x4 0.50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
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STw4141 pinout
STw4141
1
Figure 1.
STw4141 pinout
Pin assignment in TFBGA 3x3 mm - 16 bumps 0.5 mm pitch
1 1 AA BB CC DD
22
3 3
4 4
4 4
3 3
2 2
1 1 A A B B C C D D
PGND
VLX1
VLX2
VOUT1
VOUT1
VLX2
VLX1
PGND
PVDD
STATE
T_MODE
VOUT2
VOUT2
T_MODE
STATE
PVDD
MODE/ SYNC
AUTO
VSEL
GND
GND
VSEL
AUTO
MODE/ SYNC
FB1
FB2
VDD
EN
EN
VDD
FB2
FB1
Top view
Bottom view
Table 1.
Pin A1 B1 C1 D1 A2
STw4141 pin description
Symbol PGND PVDD MODE/SYNC FB1 VLX1 Power ground Power supply voltage MODE/SYNC = High to forced PWM mode MODE/SYNC = Low to forced PFM mode MODE/SYNC = 600 kHz - 1.5 MHz external clock synchronization in PWM Feedback 1 External inductor connection pin 1 Output STATE pin allow the user to monitor operation mode of the product STATE = High - PFM mode STATE = Low - PWM mode If not used must be left unconnected. PWM/PFM automatic switch control pin AUTO = High - PWM/PFM mode automatic switch ENABLED AUTO = Low - PWM/PFM mode automatic switch DISABLED PWM/PFM mode controlled by MODE/SYNC pin) Feedback 2 External inductor connection pin 2 Input signal for test mode selection. This pin must be connected to GND. Voltage selection input VSEL = High - VOUT1 = 1.8V, VOUT2 = 1.2V (valid for STA1) VSEL = Low - VOUT1 = 1.8V, VOUT2 = 1.0V (valid for STA1) (For other voltage options see Table 1: STw4141 ordering information) Signal supply voltage Output voltage 1 Description
B2
STATE
C2
AUTO
D2 A3 B3
FB2 VLX2 T_MODE
C3
VSEL
D3 A4
VDD VOUT1
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STw4141 Table 1.
Pin B4 C4
STw4141 pinout STw4141 pin description (continued)
Symbol VOUT2 GND Output voltage 2 Signal ground Enable Input: EN = Low - Device in shutdown mode, EN = High - Enable device This pin must be connected either to VDD or GND. This is the ground pin related to power signal. This pin should be connected to the board ground plane by short and wide track or multiply vias to reduce impedance and EMI. This is the ground pin related to analog signal. Description
D4
EN
PGND pin GND pins PVDD pin
This pin is designed to provide power to the device. This path leads high currents. It should be wide and short to minimize track impedance to reduce losses and EMI. This pin is designed to provide signal supply voltage to the device. There is no specific VDD pin requirement for its related track design. VLX1/VLX2 pins External coil is connected on those pins. It should be placed as closed as possible to the device in order minimize resistances which cause looses. These paths lead high currents. It is the first output voltage of this device. This path leads high currents. It should be wide and VOUT1 pin3 short to minimize track impedance to reduce losses and EMI. It is the second output voltage of this device. This path leads high currents. It should be wide and VOUT2 pin short to minimize track impedance to reduce losses and EMI. FB1 pin FB2 pin ENABLE pin Intended to measure VOUT1 voltage in order to ensure the regulation of this output. Intended to measure VOUT2 voltage in order to ensure the regulation of this output.
This is the enable pin of the device. Pulling this pin to ground, forces the device into shutdown mode. Pulling this pin to VDD enables the device. This pin must be terminated. MODE/SYNC pin The MODE/SYNC pin is a multipurpose pin which provides mode selection and frequency synchronization. The device can also be synchronized to an external clock signal from 600 kHz to 1.5 MHz by the MODE/SYNC pin. During synchronization, the mode is forced to PWM mode and the top switch turn-on is synchronized to the rising edge of the external clock. This pin allows the device to automatically switch from PWM to PFM mode following load on both AUTO pin 2 outputs. STATE pin VSEL pin This output pin informs user in which state the device is working: PWM or PFM mode. This pin is used to reduce VOUT2 (CORE) output voltage in order to reduce the processor power consumption when entering into sleep mode.
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Electrical characteristics
STw4141
2
2.1
Electrical characteristics
Absolute maximum ratings
Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltages are referenced to GND. Table 2.
Symbol PVDD VDD VEN VSEL VMODE/SYNC VAUTO VT_MODE VSTATE VOUT1,FB1 VOUT2, FB2 VLX1 VLX2 TA TJ TSTG
Absolute maximum ratings
Parameter Power supply voltage Signal supply voltage Enable input Voltage selection Operating mode selection/synchronization input PWM/PFM automatic switch selection Test mode selection Operating mode information Output voltage 1, feedback 1 Output voltage 2, feedback 2 External inductor connection pin 1 External inductor connection pin 2 Operating temperature range Maximum operating junction temperature Storage temperature range Value -0.3 to 6 -0.3 to 6 -0.3 to VDD -0.3 to VDD -0.3 to VDD -0.3 to VDD -0.3 to VDD -0.3 to VOUT1 -0.3 to 3.3 -0.3 to 3.3 -0.3 to VDD -0.3 to 3.3 -40 to 85 150 -65 to 150 Unit V V V V V V V V V V V V C C C
2.2
Thermal data
Table 3.
Symbol RthJA
Thermal data
Parameter Thermal Resistance Junction-Ambient TFBGA 3x3 mm - 16 bumps - 0.5 mm pitch Value 150 Unit C/W
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STw4141
Electrical characteristics
2.3
DC electrical characteristics
Characteristics measured over recommended operating conditions unless otherwise is noted. All typical values are referred to TA = 25C, PVDD = 3.6V, VDD = 3.6V.
Table 4.
Symbol PVDD ILIM VOUT1(1)
DC electrical characteristics
Parameter Power supply voltage Peak current limit Output voltage 1(2) Output voltage 2(2) VSEL = VDD, MODE/SYNC = VDD VSEL = GND, MODE/SYNC = VDD -3 -3 -3 Test Conditions Min. 2.7 1.6 +3 +3 +3 200 400 IOUT1 = 0 mA, IOUT2 = 0 mA EN = VDD, VSEL = VDD MODE/SYNC = VDD, AUTO = GND IOUT1 = 0 mA, IOUT2 = 0 mA EN = VDD, VSEL = VDD MODE/SYNC = GND, AUTO = GND EN = GND, VSEL = GND MODE/SYNC = GND, AUTO = GND Typ Max. 5.5 Unit V A % % % mA mA
VOUT2 Output voltage 2(2) IOUT1 IOUT2 Output current 1 Output current 2 Quiescent current (PWM)
600
A
Iq
Quiescent current (PFM)
90
A
Shutdown current
1
5
A
Enable functions VENH VENL Enable threshold high Enable threshold low 0.9 0.4 V V
Mode/sync functions VM/SH VM/SL MODE/SYNC threshold high MODE/SYNC threshold low 0.9 0.4 V V
VSEL functions VSELH VSELL Voltage selection threshold high Voltage selection threshold low 0.9 0.4 V V
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Electrical characteristics Table 4.
Symbol Auto functions VAUTOH VAUTOL Voltage selection threshold high Voltage selection threshold low 0.9 0.4
STw4141
DC electrical characteristics (continued)
Parameter Test Conditions Min. Typ Max. Unit
V V
State functions VSTATEH VSTATEL
1.
Voltage selection threshold high Voltage selection threshold low
RLmax = 100k, CLmax = 10pF RLmax = 100k, CLmax = 10pF
0.7VOUT1 0.3 VOUT1
V V
VOUT1 VOUT2 . This condition must always be valid.
2. Output voltage accuracy excludes line and load transients
2.4
Dynamic electrical characteristics
Characteristics measured over recommended operating conditions unless otherwise is noted. All typical values are referred to TA = 25C, PVDD = 3.6V, VDD = 3.6V.
Table 5.
Symbol fSW fSYNC Ts TS2
Dynamic electrical characteristics
Parameter Switching frequency Sync mode frequency Settling time (soft start) Settling time VSEL change from GND to VDD VOUT2 (reduced)/VOUT2 600 400 80 Test Conditions Min. Typ 900 1500 Max. Unit kHz kHz s s
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STw4141
Electrical characteristics
2.5
Soft start
To avoid spikes on battery during STw4141 start-up sequence, a smooth start-up is implemented. Reference voltage grows up less than 600 s until it achieves is final target. Therefore, STw4141 start up is smooth and secure for the overall mobile phone.
Figure 2 illustrates a smooth start up sequence where VIN = 3.6V, VOUT1 = 1.8V@ 200mA, VOUT2 =1.2V@400mA.
Figure 2. Smooth start-up sequence
2.6
Settling time of VOUT2
Figure 3. Settling time of VOUT2, IOUT1 = 200mA, IOUT2 = 400mA
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Electrical characteristics
STw4141
2.7
Line transients
Figure 4. Line transient, VOUT1 = 1.8V @ 100mA, VOUT2 = 1.2V @ 100mA
2.8
Load transients in AUTO mode
Figure 5. Load transient in AUTO mode VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V
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STw4141
Electrical characteristics
2.9
Figure 6.
Load transients in PWM mode
Load transient in PWM mode, IOUT1 = 1mA to 200mA, IOUT2 = 1mA to 400mA
Load transient output 1 leading output 2 VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V Load transient related to in-phase switching VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V
Load transient output 2 leading output 1 VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V
Load transient related to anti-phase switching VIN = 3.6V, VOUT1 = 1.8V, VOUT2 = 1.2V
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Electrical characteristics
STw4141
2.10
Switching between PFM and PWM in FORCED mode
Figure 7. Switching between PFM to PWM - VIN = 3.6V, IOUT1 = 10mA, IOUT2 = 10mA
Figure 8.
Switching between PWM to PFM - VIN = 3.6V, IOUT1 = 10mA, IOUT2 = 10mA
14/30
STw4141
Electrical characteristics
2.11
Efficiency in PWM
The efficiency of a switching regulator is equal to the total output power divided by the input. STw4141 has high efficiency up to 92% (for the 2 outputs). Efficiency curve is flat over the output current range.
Figure 9.
Switching regulator efficiency in PWM mode
Efficiency in PWM mode @ VIN=2.7V, TA= 25C Efficiency in PWM mode @ VIN=3.6V, TA= 25C
100
100
90
90
80
80
70 60 50 40 30 20 200 180 160 140 120 100 280 40 120 40 1 1 80 20 200 10 0 360 400 320
70
Efficiency (%)
90-100 80-90 70-80 60-70 50-60 40-50 30-40 20-30 10-20 0-10
60 50 40 30 20 200 180 160 140 120 100 160 40 1 40 1 80 20 120 200 10 0 320 360 400
Efficiency (%)
90-100 80-90 70-80 60-70 50-60 40-50 30-40 20-30 10-20 0-10
160
IOUT2 (mA)
IOUT1 (mA)
60
Efficiency vs IOUT1@IOUT2 PWM mode, TA=25C
100
Efficiency vs IOUT1@IOUT2 PWM mode, TA=25C
100
VIN = 2.7V
90 80
IOUT2 = 0 mA IOUT2 = 200 mA
VIN = 3.6V
90 80 70
IOUT2 = 0 mA IOUT2 = 200 mA
240
IOUT2 (mA)
280
IOUT1 (mA)
60
240
80
80
VOUT1 = 1.8V
70
IOUT2 = 400 mA
VOUT2 = 1.2V
VOUT1 = 1.8V VOUT2 = 1.2V
IOUT2 = 400 mA
EFFICIENCY (%)
EFFICIENCY (%)
60 50 40 30 20 10 0 1 10 100 1000
60 50 40 30 20 10 0 1 10 100 1000
IOUT1 (mA)
IOUT1 (mA)
Efficiency vs IOUT2@IOUT1, PWM mode, TA=25C
100
Efficiency vs IOUT2@IOUT1, PWM mode, TA=25C
100
VIN = 3.6V
VIN = 2.7V
IOUT1 = 0 mA
90 80
IOUT1 = 0 mA
90 80
IOUT1 = 100 mA
IOUT1 = 100 mA
70
70
IOUT1 = 200 mA
EFFICIENCY (%)
IOUT1 = 200 mA
EFFICIENCY (%)
60 50 40 30
60 50 40 30
VOUT1 = 1.8V VOUT2 = 1.2V
VOUT1 = 1.8V VOUT2 = 1.2V
20
20
10
10
0
0 1 10 100 1000
1
10
100
1000
IOUT2 (mA)
IOUT2 (mA)
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Electrical characteristics
STw4141
2.12
Efficiency in AUTO
The efficiency of a switching regulator is equal to the total output power divided by the input. STw4141 has high efficiency up to 92% (both outputs) and always higher than 70% for output currents higher than 1mA.
Figure 10. Switching regulator efficiency in auto mode
Efficiency VS output currents IOUT1 and IOUT2, VIN = 2.7V, AUTO mode Efficiency VS output currents IOUT1 and IOUT2, VIN = 3.6V, AUTO mode
100 90 80 70 60 50 40 30 20 180 150 400 360 120 280 90 200 320 10 0
100 90 80 70 60
Efficiency (%)
90-100 80-90 70-80 60-70 50-60 40-50 30-40 20-30 10-20 0-10
50 40 30 20 200 160 320 360 400 120 10 0
Efficiency (%)
90-100 80-90 70-80 60-70 50-60 40-50 30-40 20-30 10-20 0-10
160
120
120
30 80 40 1 1
Efficiency VS IOUT1@IOUT2, AUTO mode, TA = 25C
100
Efficiency VS IOUT1@IOUT2, AUTO mode, TA = 25C
100
VIN = 2.7V
90 80
IOUT2 = 0 mA IOUT2 = 200 mA
VIN = 3.6V
90 80
IOUT2 = 0 mA IOUT2 = 200 mA IOUT2 = 400 mA
VOUT1 = 1.8V
70
IOUT2 = 400 mA
VOUT2 = 1.2V
70
EFFICIENCY (%)
60 50 40 30 20 10 0 1 10 100 1000
EFFICIENCY (%)
60 50 40 30 20 10 0 1
VOUT1 = 1.8V VOUT2 = 1.2V
40
1
10
80
IOUT2 (mA)
160
40
200
IOUT1 (mA)
240
IOUT1 (mA)
60
240
IOUT2 (mA)
280
80
100
1000
IOUT1 (mA)
IOUT1 (mA)
Efficiency VS IOUT2@IOUT1, AUTO mode, TA = 25C
100
Efficiency VS IOUT2@IOUT1, AUTO mode, TA = 25C
100
VIN = 2.7V
90 80
IOUT1 = 100 mA IOUT1 = 0 mA
VIN = 3.6V
90 80
IOUT1 = 100 mA IOUT1 = 0 mA
70
IOUT1 = 200 mA
70
IOUT1 = 200 mA
EFFICIENCY (%)
60 50 40 30 20 10 0 1 10 100 1000
EFFICIENCY (%)
60 50 40 30 20 10 0 1
VOUT1 = 1.8V VOUT2 = 1.2V
VOUT1 = 1.8V VOUT2 = 1.2V
10
100
1000
IOUT2 (mA)
IOUT2 (mA)
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STw4141
Electrical characteristics
2.13
Output voltages versus output currents in PWM and PFM
VOUT1 VS IOUT1 @ IOUT1 - PWM mode
1.830
1.230
Figure 11. Output voltages versus output currents in PWM and PFM
VOUT2 VS IOUT2 @ IOUT1 - PWM mode
V IN = 3.6V
1.220
VIN = 3.6V
1.820
1.810
IOUT2 = 0 mA
IOUT1 = 0 mA
1.210
VOUT1 (V)
VOUT2 (V)
IOUT2 = 200 mA
1.800
IOUT2 = 400 mA
1.200
IOUT1 = 100 mA IOUT1 = 200 mA
1.790
1.190
1.780
1.180
1.770 1 10 100 1000
1.170 1 10 100 1000
IOUT1 (mA)
IOUT2 (mA)
VOUT1 VS IOUT1 @ IOUT2 - PFM mode
1.830
VOUT2 VS IOUT2 @ IOUT1 - PFM mode
1.230
VIN = 3.6V
1.820
IOUT2 = 0 mA
VIN = 3.6V
1.220
IOUT1 = 0 mA
1.810
IOUT2 = 20 mA
1.210
IOUT1 = 10 mA
VOUT1 (V)
VOUT2 (V)
IOUT2 = 40 mA
IOUT1 = 20 mA
1.800
1.200
1.790
1.190
1.780
1.180
1.770 1 10 100
1.170 1 10 100
IOUT1 (mA)
IOUT2 (mA)
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Functional description
STw4141
3
Functional description
Introduction
The STw4141 is an easy to use, single coil dual outputs step down DC/DC converter optimized to supply low-voltage to CPUs or DSPs in cell phones and other miniature devices powered by single cell lithium-ion or 3 cell NiMH/NiCd batteries. It provides two different output voltages with high efficiency operation in a wide range of output currents. The device offers high DC voltage regulation accuracy and load transient response to satisfy demanding processor core supply. The converter is based on voltage mode buck architecture using PWM and PFM operation modes. At light load currents, the device can operate in PFM mode to maintain high efficiency over the entire load current range. Switching between PWM and PFM modes can be done automatically or can be forced by external pins (AUTO and MODE/SYNC). Externally synchronized or fixed frequency (internal oscillator) PWM mode offers full output current capability while minimizing interference to sensitive RF and data acquisition circuits.
PWM and PFM mode operation
PWM (Pulse Width Modulation) mode is intended for normal load to high load currents. Energy is delivered to the load with an accurate and defined frequency of 900 kHz. PFM (Pulse Frequency Modulation) mode is intended for low load currents to maintain high efficiency conversion. Forced mode: When AUTO pin is LOW, the operating mode is selectable by the user itself. It means that system controls the behavior of the STw4141 according to processor needs. STw4141 is switched from PWM to PFM mode using MODE/SYNC pin (refer to Section 4.1). Automatic PWM / PFM switch: When AUTO pin is HIGH, the operating mode is directly controlled by internal digital circuit according to processor needs. The device switches from PWM to PFM by itself if sum of output currents is lower than approximately 100 mA during at least 16 clock cycles. The device can be forced to PWM mode connecting MODE/SYNC to HIGH level. (see Section 2.8 and Section 2.9).
Current limiter
This protection limits the current flowing through coil. As soon as ILIM is detected, the duty cycle is terminated and prevents the coil current against rising above peak current limit. There is no reset of device.
Short circuit protection
It protects the device against short-circuit at output terminals. When one or both output voltages are decreased by 0.7 V below their nominal output values the device enters into reset followed by soft start sequence.
Thermal shutdown protection
Thermal shutdown protects the device against damage due to overheating when maximum operating junction temperature is exceeded. The device is kept in reset until junction temperature decreases by 25C approximately.
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STw4141
Application information
4
4.1
Application information
User mode details
The following table describes the different user modes available. Depending on the application constraints (processor I/O pins available) and expected efficiency, PWM or PFM mode are forced or automatically controlled by STw4141 internal digital gates. Table 6.
Mode OFF Shutdown Forced PFM FORCED Forced PWM Forced PWM and synchronized external clock Auto mode AUTO Forced PWM Forced PWM and synchronized external clock
STw4141 available user modes
User mode/pins EN L H H H H H H AUTO X L L L H H H MODE/SYNC X L H CLK L H CLK
Table 7.
Operating mode information (STATE pin - digital output)
Operation mode State pin voltage level
PFM PWM
VOUT1 GND
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Application information
STw4141
4.2
Automatic PWM/PFM mode
This user mode is designed to allow STw4141 to switch automatically between PWM and PFM modes. This feature improves the application efficiency because STw4141 enters in PFM mode according to application processor current consumption. Figure 12. Automatic PWM/PFM switch schematic example
L 4.7 H VLX1 VIN=2.7V to 5.5V CIN 10 F 6.3 V PVDD
B1 A2
VLX2
A3 A4 D1
VOUT1
APE I/O
VDD
D3
FB1
EN AUTO VSEL
COUT1 22 F 6.3 V
C1 100 nF
D4 C2 C3 C1
STw4141
B4 D2 B2 B3
VOUT2
APE CORE
FB2 STATE
MODE/SYNC
A1 C4
COUT2 22 F 6.3 V
C2 100 nF
APPLICATION PROCESSOR
PGND GND
T_MODE
MODE_INFO
SLEEP
GND
4.3
User selected PWM/PFM mode
STw4141 PWM/PFM mode can also be controlled by the application processor. This feature is accessible through MODE/SYNC pin state. It is useful to users who want to use STw4141 with the modem digital processor. Therefore, MODE/SYNC pin is connected to SLEEP mobile phone signal. Figure 13. PWM/PFM forced mode schematic example
L 4.7 H VLX1 VIN=2.7V to 5.5V CIN 10 F 6.3 V PVDD
B1 A2
VLX2
A3 A4 D1
VOUT1
APE I/O
VDD
D3
FB1
EN AUTO VSEL
COUT1 22 F 6.3 V
C1 100 nF
D4 C2 C3 C1
STw4141
B4 D2 B2 B3
VOUT2
APE CORE
FB2 STATE
MODE/SYNC
A1 C4
COUT2 22 F 6.3 V
C2 100 nF
APPLICATION PROCESSOR
PGND GND
T_MODE
MODE_INFO PWR_EN SLEEP
GND
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STw4141
Application information
4.4
External clock synchronization
Figure 14. Application using external clock synchronization
L 4.7 H VLX1 VIN=2.7V to 5.5V CIN 10 F 6.3 V PVDD
B1 A2
VLX2
A3 A4 D1
VOUT1
APE I/O
VDD
D3
FB1
EN AUTO VSEL
COUT1 22 F 6.3 V
C1 100 nF
D4 C2 C3 C1
STw4141
B4 D2 B2 B3
VOUT2
APE CORE
FB2 STATE
MODE/SYNC
A1 C4
COUT2 22 F 6.3 V
C2 100 nF
APPLICATION PROCESSOR
PGND GND
T_MODE
MODE_INFO CLK SLEEP
GND
4.5
Checking transient response versus external components
The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT is immediately shifted by an amount equal to ILOAD x ESR, where ESR is the equivalent series resistance of COUT. ILOAD also begins to charge or discharge COUT generating a feedback error signal used by the regulator to return VOUT to its steady-state value. In order to improve the transient response, it is better to use two 10 F ceramic capacitors on each output to reduce ESR.
4.6
4.6.1
Bill of Material
Inductor selection
The choice of which inductor to use depends on the price and size versus performance required with the STw4141 application. Table 7 shows some typical surface mount inductors that work well in STw4141 applications. Table 8. Bill of material: inductor selection
Supplier TDK TDK WUERTH Value (H) 4.7 4.7 4.7 RDC () 0.14 0.16 0.085 Max DC current (mA) 1100 740 900 Size (mm) WxLxH 3.5 x 3.7 x 1.2 2.6 x 2.8 x 1.2 3.8 x 3.8 x 1.8
Part number VFL4012A-4R7M1R1 VFL3012A-4R7MR74 744031004
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Application information
STw4141
4.6.2
Input capacitor (CIN selection)
Input capacitor of 10 F ceramic low ESR capacitor should be used to reduce switching losses. It should be placed as close as possible to supply pins VDD and PVDD. The connection traces should be wide and short to minimize impedance.
4.6.3
Output capacitors (COUT selection)
The selection of COUT is driven by the required ESR to minimize voltage ripple and load step transients. There are two possibilities for output capacitors: either a 22 F is connected to ground or two 10 F ceramic are used to reduce ESR and switching losses. The capacitor should be placed as close as possible to VOUTx pins. The connection traces should be wide and short to minimize impedance.
4.6.4
Capacitors selection
Table 9. Bill of Material: capacitor selection
Supplier MURATA GRM21BR60J106ME15L CIN TAIYO YUDEN TDK C2012X5R0J106MT GRM188R60J106ME47D MURATA GRM21BR60J106ME15L GRM21BR60J226ME15L JMK212BJ106MG-T COUT1, COUT2 TAYIO YUDEN JMK212BJ226MG-T C1608X5R0J106MT TDK C2012X5R0J106MT C2012X5R0J226MT JMK212BJ106MG-T C1608X5R0J106MT Part number GRM188R60J106ME47D Value 10 F, 6.3V 10 F, 6.3V 10 F, 6.3V 10 F, 6.3V 10 F, 6.3V 2 x 10 F, 6.3V 2 x 10 F, 6.3V 22 F, 6.3V 2 x 10 F, 6.3V 22 F, 6.3V 2 x 10 F, 6.3V 2 x 10 F, 6.3V 22 F, 6.3V Case size 0603 0805 0805 0603 0805 2 x 0603 2 x 0805 0805 2 x 0805 0805 2 x 0603 2 x 0805 0805
Component
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STw4141
Application information
4.7
PCB layout considerations
The Printed Circuit Board layout must include the following consideration: Current paths carrying high currents (bold lines in Figure 15) must be wide and short to minimize impedance in order to reduce looses and EMI. Small currents flow through voltage paths. No specific care is requested about voltage paths but it is recommended to follow the general rules for PCB routing to reduce influence of external and internal interferences. Figure 15. Board layout track length and width
HIGH CURRENT PATH L 4.7 H VLX1 VIN=2.7V to 5.5V CIN 10 F 6.3 V PVDD
B1 A2
VLX2
A3 A4 D1
VOUT1 FB1 COUT1 22 F 6.3 V
VOUT1=1.8V
VDD
D3
EN AUTO
D4 C2
STw4141
B4 D2 B2 B3
VOUT2 FB2 STATE COUT2 22 F 6.3 V
VOUT2=1.0V/1.2V
VSEL MODE/SYNC
C3 C1
A1
C4
PGND GND
T_MODE
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Application information
STw4141
4.7.1
PCB layout
Figure 16 and Figure 17 show the PCB layout. All components are on the top side of the board.
Figure 16. Demoboard top layer
Figure 17. Demoboard assembled with 22 F output capacitor
4.7.2
TFBGA16 internal bumps access
Pad centers are at 500 m distance. Pad diameter is 275 m. The distance between two adjacent pad edges is only 225 m. We recommend a distance for lead-out signals from the center of pad matrix by 75 m wide trace. Isolation distance in this case is 75 m (see Figure 18 and Figure 19). Figure 18. TFBGA16 ball pad spacing and track parameters to internal pads
Grid dot distance :
with A = 500m B = 275m C = 75m
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STw4141 Figure 19. PCB routing example using TFBGA16
Application information
25/30
Package outline and mechanical data
STw4141
5
Package outline and mechanical data
Table 10. TFBGA 3x3x1.20 16 F4x4 0.50. Package code: L0 - JEDEC/EAIJ
Ref A A1 A2 b D D1 E E1 e ddd eee fff 0.85 2.85 0.25 2.85 Min. 1.01 0.15 0.82 0.30 3.00 1.50 3.00 1.50 0.50 0.08 0.15 0.05 3.15 0.35 3.15 Typ. Max. 1.20 (Note 1)
Note:
1 2
Max mounted height is 1.12 mm. Based on a 0.28 mm ball pad diameter. Solder paste is 0.15 mm thickness and 0.28 mm diameter. TFBGA stands for Thin Profile Fine Pitch Ball Grid Array. Thin profile: The total profile height (DIm A) is measured from the seating plane to the top of the component. A = 1.01 to 1.20 mm Fine pitch < 1.00 mm pitch. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball there is a cylindral tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within the tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective above eee zone above. The axis of each ball must be simultaneously in both tolerance zones. Leadfree package according to JEDEC JESD-020-C
3
4
5
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STw4141 Figure 20. TFBGA 3x3x1.20 16 F4x4 0.50
Package outline and mechanical data
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Ordering information
STw4141
6
Table 11.
Ordering information
STw4141 order codes
Output voltage options(1) Package Package marking STA1 STA1 STA2 STA2 STA3 STA3 TFBGA 3x3x1.2 16 balls STA4 STA4 STA5 STA5 STA6 STA6 STA7 STA7 Packing
Part number
VOUT1(2) (I/O) 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.8 V 1.5 V 1.5 V
VOUT2 (CORE) 1.2 V 1.2 V 1.3 V 1.3 V 1.4 V 1.4 V 1.5 V 1.5 V 1.25 V 1.25 V 1.35 V 1.35 V 1.3 V 1.3 V
VOUT2reduced (CORE) 1.0 V 1.0 V 1.0 V 1.0 V 1.2 V 1.2 V 1.3 V 1.3 V 1.0 V 1.0 V 1.0 V 1.0 V 1.0 V 1.0 V
STw41411 STw41411/T STw41412 STw41412/T STw41413 STw41413/T STw41414 STw41414/T STw41415 STw41415/T STw41416 STw41416/T STw41417 STw41417/T
Tray Tape and reel Tray Tape and reel Tray Tape and reel Tray Tape and reel Tray Tape and reel Tray Tape and reel Tray Tape and reel
1. The output configuration which will be introduced in production will be only those related to customer design-in. 2. VOUT1 VOUT2 THIS CONDITION MUST BE ALWAYS VALID.
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STw4141
Revision history
7
Revision history
Table 12.
Date 24-Jan-2006
Document revision history
Revision 1 Initial release. Updates in Table 8: Bill of material: inductor selection Updates in Table 9: Bill of Material: capacitor selection Moved Ordering information to the end of the document and updated the order codes.. Changes
9-Jun-2006
2
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STw4141
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